welcome back to the channel I'm semi
Sherpa here to navigate you through the
intricate world of semiconductor
Technologies
diving deeper into our photo lithography
series episode 3 promises a richer and
more diverse exploration
whether you're aiming for academic
discourse professional dialogues or just
a chat with field experts this series
equips you with the insights you need
it's tailored for everyone from veteran
Engineers to budding enthusiasts
today we Spotlight alignment leveling
and overlay in lithography
we'll demystify the fundamentals of
alignment and leveling drawing insights
from asml's twinscan system and then
journey into the nuances of overlay
measurement and control
and there's more on the horizon upcoming
episodes will delve into CD control
photomask photochemicals euv and
multi-patterning Technology
in this installment we'll kick off with
an overview of alignment and overlay
transition into the workings of asml's
twinscan system and then Deep dive into
overlay control
to conclude we'll provide a visual mind
map to encapsulate the episode's essence
so brace yourself for an enlightening
Expedition into lithography's alignment
and overlay realms
ready to dive in let the exploration
begin
overlay is a term that describes the
layer to layer X Y placement error in
the process of semiconductor
Manufacturing
it's also commonly referred to as
misalignment or pattern X Y position
error
this concept is a critical performance
indicator for lithography scanners which
are essential Tools in semiconductor
fabrication
unlike registration which is about the
alignment of the lithographic pattern to
an absolute coordinate grid overlay
focuses on the accuracy of a new pattern
printed over an existing one on a
semiconductor wafer now why is overlay
so important
in modern semiconductor processes
transistors have become incredibly small
often just several nanometers in size
this makes it crucial for each layer of
an integrated circuit or IC to align
perfectly with the layers below it often
to within a margin of just one nanometer
any deviation from this precise
alignment can significantly impact the
electrical conductivity between layers
leading to poor performance of the final
device
integrated circuits are built through a
series of patterning steps and each new
layer must align precisely with the
existing ones to ensure the IC functions
as intended
overlay control is as critical as
controlling the dimensions of the
semiconductor features
even a slight misalignment can lead to
electrical issues like shorts or opens
severely affecting the device's
performance and reliability
for example at the gate level overlay
errors can cause an increase in leakage
current
at the contact or via level these errors
can lead to higher contact resistance or
even incorrect electrical connections
as devices become more integrated in
patterns finer the minimum overlay
margin is shrinking making the
continuous Improvement of overlay
increasingly critical
overlay errors can occur due to subtle
changes and components of the exposure
system like the alignment system
projection lens and illumination system
or due to inconsistencies in the wafer
surfaces
moving on to Overlay measurement
Metrology plays a vital role in
monitoring overlay performance and
process control
after the photolithography process
overlay measurement is performed to
check the alignment
during this process alignment and
overlay marks are used
these are typically located in the
Scribe Lane at the boundary between dies
it's important to clarify that alignment
marks originate from the previous layer
while overlay marks are generated during
the exposure of both the current and the
previous layers these marks are later
removed in the final packaging stage
during the sawing process for chip
dicing key performance indicators for
overlay measurement include the center
difference between overlay markers which
yields DX and Dy values
these are then represented in a vector
map
a commonly used metric is mean plus
three sigma which considers both the
average error and the standard deviation
of overlay values
in summary overlay is a critical
parameter in semiconductor manufacturing
affecting the yield performance and
reliability of the final integrated
circuits accurate overlay measurement
and stringent control mechanisms are
therefore indispensable in the entire
icy fabrication process in the intricate
world of integrated circuit or IC
manufacturing the planar process
involves a comprehensive set of
procedures each push to its
technological limits
lithography is not just a step but a
Cornerstone in icy manufacturing
influencing three critical performance
indicators resolution overlay and
throughput of semiconductor chips
overlay is especially critical because
it describes the alignment deviation
between patterns on neighboring layers
of a semiconductor wafer
this alignment is not just a technical
specification it's a determinant of the
quality of the integrated circuit and a
significant constraint for achieving
High device yield in semiconductor
Manufacturing
if the overlay exceeds a certain limit
the consequences can be catastrophic
leading to short circuits open circuits
and various other types of faults
the industry is continuously evolving
and the standards for overlay are
becoming increasingly stringent
according to the international roadmap
for devices and systems irds lithography
roadmap of 2021 the overlay tolerances
are tightening
for example the overlay three sigma for
Dram was 3.6 nanometers for an 18
nanometers node in 2018.
fast forward to 2030 and it's expected
to be less than two nanometers for a sub
10 nanometers node
these overlay three sigma values are
what we refer to as on product overlay
opio measured at the wafer level after
the etching process
these opo values set the Benchmark for
what the actual lithography equipment
known as single machine overlay Smo must
achieve
the acceptable levels for Smo are
generally about 30 of the opo levels
in terms of measurement equipment the
total measurement uncertainty tmu is
developed with a budget Target that's
just one tenth of opio making it
incredibly precise
now let's talk about the role of
lithography systems in meeting these
stringent overlay requirements
asml a leading provider of lithography
systems offers euv machines like the
twinscan nxe 3400c with a dedicated
Chuck overlay dco of 1.4 nanometers and
a match machine overlay MMO of 1.5
nanometers
another dpv model the twinscan NXT 2100i
has even more impressive specifications
with a single machine overlay Smo of 0.9
nanometers and an MMO of 1.3 nanometers
these machines are critical for meeting
the overlay requirements for advanced
logic nodes and dram devices which are
continuously evolving from an economic
standpoint better overlay control
translates into smaller die sizes which
means more dive per wafer and ultimately
a lower cost per die
this economic incentive makes it
imperative that overlay specifications
must continuously evolve in lockstep
with device geometries
on the design side initial layouts are
made to be less sensitive to expected
overlay errors
however as overlay control improves
these designs can be further
miniaturized which only emphasizes the
need for continuous advancements in
overlay measurement and control
to sum it up overlay is not just a
technical specification it's a critical
parameter in semiconductor Manufacturing
its importance is only growing as
technology nodes advance
the industry is pushing the boundaries
and lithography systems especially those
from asml are at the Forefront of this
technological advancement
with feature sizes getting smaller the
overlay tolerances are also tightening
making the role of accurate overlay
measurement and control more crucial
than ever in semiconductor manufacturing
overlay control is a critical factor
that directly impacts the yield and
performance of the chips produced
two key metrics in overlay control are
single machine overlay Smo and on
product overlay opio
is considered the gold standard for what
a single lithography tool can achieve in
terms of overlay control
it's a critical metric used to assess
the inherent ability of a lithography
tool to align layers precisely during
the photolithography process
this becomes especially important for
advanced nodes like three nanometers
where the tolerances are extremely
narrow often in the single digit
nanometer range
on the other hand opio is the overlay
error measured on a wafer after it has
undergone the complete photo lithography
and etching processes
this is typically assessed during the
after etch inspection AEI
interestingly even when a machine has
excellent Smo levels the opio can often
exceed acceptable limits sometimes going
Beyond six nanometers as shown below
this discrepancy arises due to a variety
of factors such as Match Machine overlay
MMO alignment accuracy and errors
introduced at various stages like
deposition
etching and CMP processes
additionally war page changes during the
etch process can also contribute to this
particularly in complex devices like 3D
nand
as a result the industry is increasingly
relying on AEI to capture these
variances
to address these challenges the industry
adopts a holistic approach aimed at
minimizing overlay errors throughout the
entire chip manufacturing process
this approach is comprehensive focusing
on both Smo and upo and takes into
consideration all contributing factors
and processes
several key components make up this
holistic approach
first it emphasizes the systematic
optimization of all relevant processes
and devices
this ensures that each step in the
manufacturing process is fine-tuned for
optimal overlay control
second when the lithography tool alone
can't correctly overlay the approach
allows for modifications to the
photomask providing an additional layer
of control
feedback mechanisms are another crucial
element
these systems particularly those that
correct after develop inspection to
after etch inspection ADI to AEI overlay
skew are integrated with automatic
process control
this enables real-time adjustments and
fine-tuning enhancing the overlay
accuracy
peripheral processes such as deposition
etching and CNP are also meticulously
optimized
the goal here is to minimize any
asymmetry in the alignment and overlay
Keys thereby reducing the potential for
error
Advanced modeling techniques are
employed for overlay correction
including the use of specialized wafer
alignment models that are based on wafer
alignment model mapping overlay
Metrology is seamlessly integrated into
the fabrication process
this allows for continuous monitoring
and adjustment of the lithography tools
settings ensuring that the overlay
specifications are consistently met
the approach goes beyond just immediate
Corrections
it includes a thorough error
decomposition process that breaks down
the total overlay budget into different
components
these are then categorized into
systematic and non-systematic errors
allowing for more targeted control
measures
by integrating these multiple
interrelated components the holistic
approach aims to meet the increasingly
stringent overlay specifications
required in modern semiconductor
manufacturing improving on product
overlay opo through a holistic approach
necessitates a deep understanding of the
classification and hierarchy of overlay
this knowledge is pivotal for
systematically analyzing the budget of
overlay errors pinpointing their Origins
and formulating effective Improvement
strategies
in terms of overlay classification the
total overlay on a wafer is essentially
the on product overlay opio
this reflects the final overlay
performance of the lithography process
incorporating both customer structures
and various process effects
total opo is a composite metric that
includes single machine overlay Smo
mixed machine overlay MMO litho opo
long-term stability opo and process opio
different methods for classifying
overlay have emerged to cater to various
research needs
these classifications arise from
different aspects like error sources
quality control measures and correcting
models
quality control and IC manufacturing is
intricately linked to Overlay at
multiple levels
these levels include within dye overlay
die to die overlay wafer to wafer
overlay Check to Check overlay and lock
a lot overlay
each of these levels reflects specific
dimensional features of overlay
variations
they are correlated and consistent due
to the stable yet imperfect properties
of the manufacturing devices that handle
the Wafers and the processes that the
Wafers undergo
when it comes to Overlay hierarchy
lithographers aim to characterize
overlay errors for the purpose of making
improvements
overlay errors can be viewed
hierarchically starting with the most
fundamental errors
these occur when a single stepper is
used in conjunction with ideal
substrates that provide High
signal-to-noise alignment signals
this basic set of overlay errors is well
captured by overlay models
when more than one stepper is involved
an additional set of overlay errors
known as matching errors comes into play
Beyond these there are process specific
contributions to Overlay which can
result in non-ideal alignment targets
and changes in wafer shape
understanding overlay errors in terms of
a hierarchy allows for a comprehensive
accounting which is invaluable for
assessing and improving overlay
this hierarchical understanding is
integral to the holistic approach aimed
at enhancing opo in semiconductor
Manufacturing
asml story is one of both Innovation and
a commanding 91 market share in the
world of lithography systems for
Semiconductor Manufacturing
the trajectory of this high-tech leader
is punctuated by technological Marvels
and critical breakthroughs that have
redefined the chip manufacturing
landscape
now let's take a closer look at how the
company's dual stage twinscan systems
Have Been instrumental in securing its
top tier industry position
founded as a technology offshoot of
Phillips in 1984 asml hit the ground
running by launching its first
commercial stepper the POS 2010's G line
in 1985. it was during this time that
the company began shaping its initial
expertise in photolithography
but it was the introduction of the POS
5500 platform in the early 1990s that
really enabled asml to come into its own
in 2000 asml unveiled its twinscan
platform equipped with pioneering dual
stage technology
this wasn't just a step up it was a
complete Game Changer
by October 2001 tsmc had installed the
first system and by 2002 asml had
LeapFrog Nikon to become the number one
litho tool supplier despite intense
competition
continuing to strengthen its Market
position asml introduced immersion ARF
lithography in 2007 in euv technology in
2019
the dual stage twinscan system solved
the throughput limitations of earlier
single stage systems boasting a
substantial 40 increase in throughput
this efficiency was achieved by
separating the measure side and the
exposed side of the process
in this way while one wafer is being
exposed another is simultaneously loaded
aligned and mapped
such parallel operations keep the
expensive lens system on the exposed
side constantly active maximizing its
utility
this setup ensures that the measure
sequence duration is always shorter than
the exposed time ensuring a wafer is
always ready for exposure
Additionally the dual stage technology
provides real-time error correction
prior to exposure
critical data from the measure side
feeds into the exposed side to mitigate
X Y overlay errors and Z Focus errors
vital for enhancing resolution and
Precision in the twinscan Metrology
process the ultimate aim is to minimize
XYZ errors between the aerial image and
the wafer this is accomplished through a
variety of sensors and measurement
methods such as level sensor for Z
errors smash sensor for XY errors and
the tis sensor to account for both
reticle and Stage errors in all three
dimensions the geometric data obtained
shortly before is used to position the
wafer under the projection lens as
accurately as possible using six degrees
of freedom today asml's Pinnacle of
productivity is the twinscan NXT 2100i
an immersion ARF tool that boasts an
exceptional throughput of 295 Wafers per
hour in a remarkable single machine
overlay of 0.9 nanometers thanks to its
Advanced twin scan technology
in summary asml's position as an
industry leader is underpinned by its
unyielding dedication to Innovation
especially in the realm of dual stage
technology the scanner commonly achieves
a throughput of 175 Wafers per hour
which translates to a processing time of
just 20 seconds per wafer or 0.2 seconds
for each exposure
to put this into perspective the
exposure time is faster than the blink
of an eye which takes about 0.3 to 0.4
seconds
standard way for scan speeds during
exposure range from 0.6 to 1 meter per
second
while these speeds may seem comparable
to a person walking briskly or jogging
it's crucial to remember that the
scanner maintains this pace while
achieving nanometer level precision
High accelerations between 20 and 40
meters per square seconds are required
to attain these speeds these
acceleration rates are two to four times
the acceleration due to gravity of 9.81
meters per square seconds akin to a car
going from 0 to 60 miles per hour in
just a couple of seconds
however these high accelerations can
introduce vibrations that interfere with
the machine's nanometer scale
positioning accuracy in addition reticle
motion is generally four times faster
necessitating even higher accelerations
these rapid movements are typically
powered by linear motors which exert
reaction forces as large as 5000 to 10
000 newtons on the support structure
to give you an idea of this Force it's
equivalent to 10 to 20 people pushing
against a wall simultaneously
to maintain this level of precision The
Machine's Dynamic design isolates these
substantial reaction forces from the
position measurement systems and
projection Optics any residual
vibrations must be damped by the stage
control systems after the acceleration
phase the stage is allowed a few
milliseconds to achieve nanometer level
scanning accuracy which is like
pinpointing a single grain of sand on an
entire Beach
as shown in the accompanying figure the
asml twinscan scanner is a Marvel of
engineering designed to tackle complex
challenges
its robust base frame is not just
anchored to the floor it's engineered to
absorb the substantial reaction forces
that are generated when the stage moves
the first line of defense against
instability comes from air mounts they
are pneumatic Springs that do more than
just support the Metro frame
this Metro frame is the backbone that
holds critical systems like the stage
position measurement and the projection
Optics
the air mounts serve a dual purpose they
not only provide support but also act as
a barrier against floor vibrations
ensuring that the Metro frame remains
stable
but the Quest for stability doesn't end
there
the projection Optics are further
stabilized by active damping mechanisms
commonly known as piezoactive lens
mounts or Palm
these mechanisms make sure that the
internal elements of the lens are not
just stable but remain completely
undisturbed which is crucial for the
accurate tracking of the lens by the
stage let's talk about the reticle and
Illuminator they are strategically
placed on a table that's directly
attached to the Metro frame the top part
of the Illuminator is also connected to
this Frame however the bottom modules
are connected to a separate external
frame and that's done for practical
engineering reasons
the wafer table or what's technically
known as the mirror block is another
Masterpiece mirrors are mounted on the
sides of the wafer stage to monitor its
translation and rotation for controlling
the six degrees of freedom the change in
position of these sides is measured with
an interferometer as the wafer stage
moves the detected intensity changes
from dark to Bright and vice versa as a
function of the relative position of the
one mirror on wafer stage and the other
reference Mirror by precisely reading
the intensity the position of the moving
mirror can be evaluated to better than
Lambda over 64. the mirror on wafer
stage is supported by what's called an
air foot
this air foot is connected to balance
masses allowing the mirror block to
literally float on a cushion of air
adding yet another layer of stability to
the system when it comes to Stage motion
the system uses a dual stroke approach
the Short Stroke is fine-tuned to
operate at sub nanometer levels of
precision while the long stroke works at
the micrometer level
the Staters of the long Stroke motor
work in Synergy with either a balanced
mass or a magnetic plate bringing
stability to the entire system
reaction forces are cleverly redirected
to these balance masses further
minimizing any disturbance forces that
could affect the Metrology frame
in summary the asml twinscan scanner is
nothing short of an engineering Wonder
it employs a multi-layered approach to
stability from vibration isolation and
precise stage motion to intricate
alignment mechanisms in photolithography
two critical aspects must be managed the
correct pattern size and the precise
alignment of these patterns across
multiple process steps alignment is the
meticulous positioning of the wafer
before the exposure process starts its
main goal is to reduce overlay errors
between the current and previous layers
on the wafer to achieve this alignment
marks etched onto the wafer scribe line
during previous lithography steps are
read using specialized Optics
the data collected from these marks is
then used to determine the wafer's exact
position magnification and rotation
this data is also cross-referenced with
the wafer map from the previous layer to
ensure accurate overlay
mathematical and statistical analyzers
are then performed on the collected data
to align the reticle or aerial image
with the wafer pattern
this alignment is done before the
exposure phase for every wafer and
focuses specifically on inner field
alignment
the asml twinscan system is designed to
handle both alignment and leveling tasks
it has two main components the measure
side and the exposed side
the measure side aims to get the aerial
image and the wafer perfectly lined up
to reduce errors in all three dimensions
X Y and Z all Wafers go through the
alignment process on the measure side
the exposed side on the other hand
focuses on aligning the wafer stage with
the aerial image of the reticle
the goal is to position the wafer
correctly relative to both the wafer
stage and the aerial image this dual
approach ensures High Precision in both
the setup and the actual exposure
process
the data from the alignment and leveling
processes are then used to guide the
exposure process
this is crucial because the lens systems
used are expensive and any measurement
delays that lead to idling are
unacceptable
therefore the measurement time must be
shorter than the exposure time
High productivity systems like the NXT
2050i can measure up to 55 alignment
marks at a rate of 295 Wafers per hour
for 10 nanometers dram products which
have about 110 shots on a 300
millimeters wafer measuring all Fields
is often impractical so only about half
are measured
the system measures only inner field
values from the alignment marks and uses
them to ensure proper way for alignment
during exposure
for enterfield alignment overlay values
from the previous layer are used
leveling is another critical process
that ensures the wafer surface is in the
optimal focal plane of the projection
lens during exposure
given the varying topographies of Wafers
leveling is vital for aligning the wafer
surface with the lens system's focal
plane in asml equipment interferometers
or encoders are used to establish a
reference plane
light is reflected at an oblique angle
onto the wafer and the polarization
changes and the reflected light are
detected and calculated to determine
leveling requirements
a leveling map or Z map is generated
after scanning the entire wafer which
identifies Focus vulnerable areas
the equipment compensates for these
areas within its operational range
before exposure
this Z map is crucial for minimizing
defocus and outlining the exposure
profile
changes in Z values can also affect X Y
alignment typically causing about
one-tenth of the level of X Y value
changes before modeling any anomalies in
the data are repaired linear fitting is
applied in the X Direction and moving
Focus optimization is applied in the y
direction which is the scanning
Direction
the optimize set points are then fitted
with fourth degree polynomials for
precise control additional factors like
blue Focus lens heating z-off sets lens
to stage offsets and zeroing errors are
also taken into account to ensure the
highest level of accuracy in leveling
various sensors are used on both the
measure and exposure sides to achieve
minimum overlay and focus errors
on the measure side sensors like
interferometers zero sensors Smash and
level sensors are used for wafer
alignment and leveling on the exposure
side interferometers zero sensors tis
ileus and spot slit sensors are used for
lens aberration optimization and reticle
alignment overall the system aims for
the highest level of accuracy in both
alignment and leveling which is
essential for high yield and performance
in integrated circuits for high
Precision 38 nanometer half pitch
lithography the system imposes stringent
constraints moving average ma errors
must be confined to about one nanometer
and moving standard deviation MSD errors
to about 7 nanometers these metrics
represent the average and standard
deviation of stage positioning errors
during exposure respectively Focus
errors which occur in the Z Direction
parallel to the lens's optical axis also
contribute to Imaging and accuracies
however these Focus errors can typically
tolerate a 10-fold increase compared to
horizontal positioning errors the dual
stage design of the scanner epitomizes
efficiency it employs two wafer stages
that operate in tandem to measure and
expose Wafers thereby reducing idle time
and enhancing alignment capabilities
the measurement sequence is
intentionally shorter than the exposure
time to ensure a wafer is always ready
for exposure
this operational principle is the
Bedrock of asml's twin scan technology
optimizing throughput while minimizing
lens system downtime
let's explore the Journey of a wafer in
the twinscan system as Illustrated in
the accompanying figure
the system employs a dual Chuck wafer
stage to boost productivity via a
swapping mechanism
on the measure side the process is as
follows
load the pre-coded wafer is transferred
from the track to the measure side's
Chuck zeroing initial positioning
establishes the Chuck's relative
location to the stage stage align the
system pinpoints the Chuck's exact
position and elevation Global level
Circle GLC the Step at the wafer Edge is
identified crucial for precise alignment
course wafer align Cowa preliminary
alignment captures some alignment marks
within a 44 micrometers range z-map a
comprehensive height map of the wafer is
generated through leveling measurements
find wafer align fiwa all alignment
marks are located according to the
recipe to correct any misalignments swap
the wafer is now primed for swapping
with an exposed wafer on the exposed
side
on the exposed side the steps include
zeroing the wafer's position is
reascertained reticle stage align
synchronization occurs between the
reticle and wafer positions lot
correction Loco lens aberrations are
rectified via stage sensors reticle
align the final alignment step
harmonizes the reticle and wafer
positions expose the exposure process
relies on the previously measured
alignment and height data Swap and
unload the exposed wafer is swapped with
a new one from the measure side then
unloaded and returned to the track for
development
this comprehensive overview highlights
the asml twin scan scanners engineering
Marvel briefing each critical process on
both the measure and exposed sides now
let's take a closer look at each
critical process on both the sides to
understand this intricate workflow
ensuring seamless Transitions and
unparalleled efficiency in semiconductor
manufacturing accurate stage positioning
is crucial in the alignment process of
twinscan operation
there are two primary methods to ensure
this accuracy the interferometer and
encoder methods interferometers have
been the industry standard for over
three decades
they operate by measuring the optical
path difference between a beam reflected
on a stage mirror and an internally
reflected beam these beams create an
interference pattern the fringes of
which can be counted to calculate the
change in the length of the external
beam in terms of parts of the wavelength
and Air
however this method has its limitations
it is sensitive to changes in the
refractive index of the air leading to
measurement noise and errors
particularly in the 0.5 to 50 hertz
frequency range even in well-conditioned
systems these errors can exceed one
nanometer
as an alternative the encoder method
offers greater stability especially in
reducing noise
unlike interferometers encoders feature
short vertical fixed beam path lengths
sometimes as short as 15 millimeters
while still accommodating a horizontal
travel range in the operational plane of
hundreds of millimeters
this design significantly minimizes
sensitivity to refractive index changes
the sensing part of the encoder is
connected to the Chuck and measures
relative to a grating
this grading is supported by a grid
frame mounted on a vibration isolated
Metrology frame providing a stable
reference point known as The Quiet
stable world
the process of zeroing aligns the stage
to this quiet stable Metrology frame
world and serves two main purposes
when a wafer is loaded onto the system
the wafer stage WS is controlled using
the encoder method the goal is to
establish a zero point or reference
point for controlling the Ws laying the
foundation for the accuracy of all
subsequent steps in this Step Zero
sensors measure the mirror block of the
wafer stage to confirm its x y z
positions and rotations in RX Ry and RZ
ensuring that the measure side has its
own accurate reference point
the shift from the interferometer-based
measurement of the XD system to the
encoder-based design of the NXT twinscan
system represents a significant Leap
Forward in both overlay accuracy and
throughput efficiency
here's how these improvements have been
achieved first the NXT twinscan system
enhances overlay accuracy through its
innovative design of situating an
encoder grid frame on a vibration
isolated Metrology frame creating an
ultra stable quiet world
this framework not only serves as a
stable base but also houses the exposure
lens and other critical measuring
equipment
composed of a rigid zero expansion
material carrier and four mounted grid
plates the grid frame acts as a unified
monolithic structure providing sub
nanometer level stability
this stability is maintained over
thermal time constants that span several
hours impacting only lower order
deformations
any such deformations are automatically
corrected for each wafer thanks to both
the stage and wafer align and an
additional inline encoder consistency
calibration
these Innovations contribute to reducing
overlay values to less than four
nanometers
second in terms of throughput the NXT
twinscan system distinguishes itself
with a significant advantage
in the older XD system two separate
zeroing actions were required one at the
measure side and another at the exposed
side leading to time-consuming processes
that affected throughput
the NXT twinscan system streamlines this
process by utilizing large planar
encoders reference to the Metrology
frame enabling continuous 2D grading
control in both measure and exposed
stages
this Innovation eliminates the need for
the second zeroing action thus making
the transition from measurement to
exposure much more efficient
consequently this efficiency translates
into a substantial increase in the
system's overall throughput capability
allowing it to process more than 200
Wafers per hour
in summary the zeroing process in asml
twinscan is a complex yet vital
operation that ensures the highest
levels of accuracy and stability in
stage positioning
it leverages Advanced methods and
meticulous design to minimize errors and
reduce noise making it an indispensable
component of semiconductor manufacturing
the reticle to wafer alignment in asml's
Twin scan systems is an indispensable
step ensuring that the pattern image on
the reticle is precisely projected onto
the wafer for exposure
this is of Paramount importance as a
single wafer can have more than 100
different image Fields requiring exact
and consistent overlay for successful
semiconductor Manufacturing
let's start with the measure side where
the overarching goal is to align the
wafer stage with a wafer itself
this is executed through a comprehensive
process managed by the advanced
alignment a a system
the AAA system oversees a series of
critical steps including zeroing stage
align GLC KOA zmap and fiwa each
contributing to the precise alignment of
the wafer stage
among these steps stage align is
particularly noteworthy in this phase
the level sensor LS measures the height
of two tis plates on the wafer stage
ensuring its vertical position is
accurately calibrated
for horizontal alignment the system
employs smash or smart alignment sensor
hybrid
smash focuses on the alignment marks on
the tis plates thereby securing the
wafer stage's horizontal position
in essence stage align is a crucial
component within the broader Advanced
alignment system which collectively
ensures that the wafer stage is
meticulously aligned in all three
dimensions x y and C through
interferometric position measurement ifm
moving on to the exposure side the
objective here is to align the reticle
with the wafer stage
the reticle features specific marks
either Paris or tis marks which are
projected onto tis plates on the wafer
stage
these plates come equipped with sensors
each containing two sensor marks used
for parallel alignment scans
the system uses extreme UV or deep UV
light to illuminate these marks and a
projection lens captures the diffraction
orders to form an aerial image the point
of highest intensity in this aerial
image is used to finalize the focus and
alignment the alignment sequence
involves four marks on the reticle
labeled R1 R2 R3 and R4
these marks are strategically positioned
above the projection lens and their
intensities are measured as the Chuck
moves in a specific pattern
once the scan is complete the point of
highest intensity is identified
finalizing the alignment
to sum it up the measure side focuses on
aligning the wafer to the wafer stage
while the exposure side aims to align
the wafer stage to the reticle the
culmination of these two processes
results in the final reticle to wafer
alignment achieving the ultimate
Metrology goal of minimizing XYZ errors
the data collected from the measure side
is instrumental for achieving this on
the exposure side
both the measure and exposure sides
utilize the same stage which is swapped
out only after the entire alignment and
exposure process is complete in this
segment we're diving into the leveling
intricacies of asml's twin scan systems
we'll examine the pivotal role of the
level sensor commonly known as LS in
leveling techniques like GLC and zmap
we'll also cover its significance in
Focus spot monitoring and the
technological shift from visible to UV
level sensors
first up is GLC short for Global
leveling Circle its primary aim is to
gauge the height of the wafer Edge to
accurately establish the scan in and
scan out points for exposure
the level sensor accomplishes this by
tracing the wafer Edge while the wafer
stage circles around
this action ensures that the wafer's
alignment Mark Falls within smash's
Focus range enhancing the Meandering
process during exposure and boosting
throughput moving on to zmap this method
is designed to generate a detailed
height map across the entire wafer
surface
initiated from a position informed by
GLC data the level sensor scans the
wafer this height map is vital for
maintaining Focus during exposure and is
continually updated for each wafer this
allows the system to remain in focus and
pinpoint areas susceptible to focus
issues enabling the equipment to make
compensations within its operational
range
the height map also doubles as a tool
for Focus spot monitoring it detects
local defocus and photo resist tearing
which can be detrimental to yield
local defocus refers to specific areas
on the wafer where abrupt topographical
changes occur often due to particles or
contamination on the wafer's backside
these anomalies can cause x y z errors
and have a significant impact on yield
the level sensor captures these
variations allowing the system to
identify and address these Focus spots
known as Chuck spots if they recur on
multiple wafers
the ongoing height mapping also enables
in-situ monitoring of photo hot spots
allowing for on-the-spot cleaning of
cross-contamination occurs thus avoiding
the need for preventive maintenance
finally let's discuss the advancements
in level sensor technology
we've transitioned from visible level
sensors which operate within a 600 to
1050 nanometers wavelength range to UV
level sensors that function within a 200
to 425 nanometers range
the UV sensors provide smaller spot
sizes and a greater number of spots
thereby improving leveling accuracy and
minimizing the impact of underlying
process layers
to sum it up the level sensor is a
Cornerstone in asml's twinscan systems
it's instrumental in GLC zmap and focus
spot monitoring
the shift from visible to UV technology
has further refined this intricate
process ensuring consistent focus and
enabling in situ monitoring capabilities
in this slide we delve into the critical
alignment processes of KOA and fiwa both
essential components of asml's twinscan
systems measurement side
first let's discuss KOA or coarse wafer
align the primary goal here is to
roughly establish the wafer's position
in terms of translation and rotation
the smash sensor is commonly employed
for this measuring two alignment marks
usually situated symmetrically around
the wafer Center
this sets a basic horizontal position on
the wafer stage within a plus or minus
44 Micron range using two valid Cola
marked pairs
these initial parameters including
translation rotation and magnification
pave the way for the subsequent fiwa
process
so how does KOA achieve this initial
alignment it utilizes the Vernier known
as principle similar to the mechanism in
Vernier calipers
this involves two tracks with periodic
divisions a master track and Anonymous
track
these tracks measure the wafer's
absolute position using 8.0 and 8.8 half
pitch patterns which repeat every 88
microns
to maintain accuracy the capture range
is confined to plus or minus 44 microns
next we move on to fiwa or find way for
a line
this is where we aim for nanometer level
precision
unlike KOA fee y uses a more extensive
set of alignment marked pairs often
dozens as specified in the recipe on the
NXT 2050s system we could measure 55
alignment marks at 295 Wafers per hour
this results in a highly accurate model
of the wafer's position which is then
employed for field-by-field Corrections
during exposure
it's crucial to clarify that field by
field correction in fee y doesn't equate
to field by field alignment while the
latter aligns each field immediately
before exposure its accuracy is
constrained by the alignment Mark
detection
for instance if the three sigma
alignment accuracy is 10 nanometers
that's the best you can achieve
any Improvement would require repeated
detection of the same marks leading to a
throughput penalty field by field
alignment is fundamentally advantageous
only when the wafer stage control is
worse than alignment noise phiwa employs
an enhanced Global alignment approach
introduced by Nikon here the entire
wafer is aligned once for Global
translation and rotation
subsequently the exposure fields are
stepped but with a closer inspection of
the alignment marks to determine the
stepping positions
this can result in higher accuracy than
field by field alignment especially when
increasing the number of fields used for
Global alignment
for instance if 13 fields are aligned
the three sigma alignment accuracy
improves to 3.4 nanometers factoring in
a two nanometer wafer positioning
accuracy enhanced Global alignment has
proven to be extraordinarily effective
and has been adopted on Commercial
scanners today as a standard alignment
scheme enhanced Global alignment gives
better overlay than field by field
alignment whenever the Precision of the
laser stage is greater than the
Precision of the scanner's ability to
capture alignment signals lastly it's
important to note that in standard
alignment processes only the wafer term
is measured and transferred to the
exposed side
this includes wafer level deformations
like translation rotation and
magnification
field terms such as the Field's own
expansion and rotation are not derived
from the alignment Mark measurements but
are feed forwarded from the overlay
measurements of the previous layer for
achieving robust alignment in
semiconductor manufacturing it's
imperative to have both a reliable
alignment Mark and a high quality sensor
capable of accurately processing the
signals asml uses primary marks or PM
for Global alignment of individual marks
for advanced technology using high order
enhancement of alignment or simply
Athena alignment system instead of
relying on an optical line edge profile
to produce an alignment signal the asml
alignment system involve the phase
grading on the wafer produced by etching
an alignment Mark into the wafer to
produce alternating phase light in
practice in the phase grading alignment
Mark the lower parts of the mark may be
filled with a different material than
that which covers the higher parts so
there may be an intensity as well as a
phase difference between the two sets of
beams
the advantages of this alignment
configuration can be summarized as
follows
first it ensures that the marker image
is always sinusoidal with a 100 contrast
irrespective of the profiles of the
process layers or any local defects in
the marker
second the high brightness of the Laser
Source coupled with phase sensitive
detection results in a very high signal
to noise ratio enhancing the reliability
of the alignment signal
the standard PM marks consist of four
separate phase gratings two of these
gratings are dedicated to alignment
along the x-axis labeled as X 8.0 and
x8.8 while the other two y 8.0 and y8.8
are for alignment along the y-axis
these specific grading significantly
extend the capture range and reliability
of the alignment system
they remain effective as long as the
alignment marks on the layers that align
to these marks are on the same side of
the wafer
asml's alignment technology has seen
significant advancements over the years
with each new generation of sensors
designed to address the limitations of
its predecessors
the Athena sensor has a large spot size
of approximately 700 micrometers
while this large spot size allows Athena
to capture signals from a more extensive
area it also presents challenges
for instance the alignment marks which
are typically around 40 micrometers wide
can be overwhelmed by noise from the
larger area that Athena captures
to mitigate the limitations of Athena
asml introduced the smart alignment
sensor hybrid or simply smash alignment
sensors
these sensors come with a smaller spot
size of about 40 micrometers and are
equipped with two additional Pro Blazers
to enhance alignment quality
one unique feature of the smash sensor
is its self-reference interferometer
which improves alignment accuracy by
mitigating the effects of process
variability this interferometer splits
the collected beam into two paths
rotates One path by 180 degrees and then
makes them interfere across a wide range
of wavelengths in 2017 asml further
Advanced its technology by replacing the
smash sensor with the Orion alignment
sensor Orion has become the standard
alignment sensor for both deep and UV
lithography systems it offers greater
accuracy and is less sensitive to
process variations that could result in
tilted alignment markers
the Orion sensor incorporates improved
Optics and mechanics featuring a dual
interferometer with dual polarization
output this design doubles the number of
output channels to eight thereby
increasing the likelihood of selecting a
wavelength and polarization that offer
high contrast and are insensitive to
asymmetry in the alignment mark
now let's delve into the Athena and
smash align marks one of the standard
marks used in Athena is the SPM Mark
which comes in various segmentation
types like ah32 a853 or ah-74
these are known as third fifth and
seventh order enhanced marks
the purpose of these designs is to
maximize signal strength and the
corresponding diffraction order thereby
increasing robustness against process
variations
for instance a fifth order enhancement
Mark will get a higher signal from the
fifth diffraction order compared to
other orders
the high order enhanced alignment Mark
is laid out in a way that the space of a
standard Mark with a 16 pitch is
subdivided into lines and spaces with a
smaller pitch increasing robustness
against CMP erosion
the Athena system is particularly
advantageous in two scenarios
first when alignment phase grading marks
are affected by polishing induced
asymmetry such as in CMP processes
Athena's ability to detect higher
diffraction orders makes it less
susceptible to errors induced by wafer
polishing
second when alignment signals are
compromised due to destructive
interference effects especially when
using coherent light sources on
transparent film Stacks or non-ideal
alignment Mark phase depths Athena's use
of two discrete and independent
wavelengths allows for more Accurate
Alignment in these cases
now let's talk about the transition from
Athena to the smash Mark which focuses
on reducing size increasing capture
range enhancing signal detection and
boosting productivity
smash has evolved into specialized
versions like smash KOA and smash XY for
more precise alignment tasks in the
smash XY system the alignment marks are
ingeniously designed at a 45 degree
angle to the sensor scan Direction
this unique design allows for the
simultaneous measurement of both X and Y
vectors in a single scan
unlike Athena where separate marks are
needed for X and Y directions smash XYZ
diagonal design enables you to double
the number of alignment marks you can
use this results in collecting twice the
amount of alignment data thereby
improving on product overlay accuracy
while maintaining the same throughput
this is a significant technological leap
over traditional systems like Athena
which required separate scans for X and
Y directions
the new Smash XY design also includes a
fast capture Mark specifically designed
to speed up course alignment
additionally this design is compatible
with sub-segmentation eliminating any
potential printability issues that could
arise from diagonal lines
moreover smash XY uses two additional
alignment wavelengths near and far
infrared for more robust Mark
integration particularly when using
opaque hard masks these multiple
wavelengths were introduced to address
situations that might be optically
unfavorable at a specific wavelength due
to low phase differences between Optical
paths or films with high Optical
absorption at that wavelength in summary
asml's alignment systems have evolved
significantly over the years with each
new sensor iteration bringing about
crucial improvements in alignment
quality
from Athena's large spot size and
susceptibility to noise to smash a
smaller spot size and self-referencing
interferometer and finally to Orion's
polarization Independence and improved
Optics each system has its unique set of
advantages and applications in this
section we're diving deep into the key
performance indicators or kpis of
alignment marks these kpis are
absolutely critical for ensuring both
the reliability and accuracy of the
alignment process in semiconductor
manufacturing first let's focus on the
mark level kpis that are measured during
the alignment process before exposure
these are wafer quality or WQ
reproducibility commonly known as Repro
and multiple correlation coefficient
abbreviated as MCC
starting with wafer quality or WQ it's a
percentage that signifies the signal
strength of the alignment Mark in an
asml exposure system
think of it as the ratio of the
intensity of the Align mark on the wafer
as read by the alignment sensor compared
to a reference point within the
equipment
the ideal reference value for WQ is 100
which would mean perfect alignment
however the recommended spec for WQ can
vary
for Athena SPM marks it should be
greater than 0.1 percent and for the
smash 3.3 system it could be as low as
0.01 percent
it's important to note that a high WQ
doesn't necessarily mean a low overlay
error it's more about the repeatability
of the readings next we have
reproducibility or Repro for short
this measures how consistently a mark
can be read ideally multiple times let's
say 25 times across the wafer
the lower the Repro value the more
reliable the measurement
this is crucial for the stability of the
tools and the accuracy of the final
Model results
moving on to the multiple correlation
coefficient or MCC
is a value that tells us how well the
alignment signal fits a sine curve the
closer this value is to one the better
as it indicates a near perfect
sinusoidal wave
this is crucial because it reflects the
quality of the alignment signal and can
even give us insights into the state of
the equipment's laser now let's
transition to the multiple wafer level
kpis which are obtained from overlay
measurements after exposure
these include the residual overlay
performance indicator or ropi and random
process noise or rpn
ropi is defined as the three sigma of
the wafer residuals of the measured
minus the modeled positions
it serves as an indicator of the
magnitude of the alignment residuals
after the alignment model has been
applied
while there's no specific recommended
spec for ropi a smaller value is
generally better rpn represents the
remaining wafer to wafer variation error
after removing the average fingerprint
from alignment residuals
here residual refers to the
uncorrectable error component and
fingerprint denotes the average residual
for each individual Mark a smaller rpn
value is desirable as it indicates less
random noise in the process now let's
talk about the current state of
alignment marks
traditional alignment marks are
relatively large compared to Overlay
targets taking up significant reticle
area
this has led to a push for Designing
narrower and smaller alignment marks to
free up valuable scribe Lane space
most chip makers are currently using
scribe lanes that are 60 micrometers to
90 micrometers wide
when designing these smaller marks it's
not just about reducing Dimensions
factors like process loading effects
inscribe Lane dummy rules also have to
be considered the innovatively designed
the combined bi-directional or CV Mark
features a compact footprint of 50 by 50
microns along with a 5 Micron exclusion
Zone on each side
this offers a significant 60 reduction
in Mark area compared to traditional
smash XY marks which measure 160 by 40
microns
this smaller footprint allows for more
marks to be placed in the Scribe Lane
which is crucial for capturing wafer
deformation fingerprints despite its
smaller size the CB Mark holds its own
in performance metrics
it works above the 0.01 threshold in
evaluations and shows comparable overlay
performance to the smash XY mark
the overlay variation can potentially
improve by up to about seven percent
with the use of more marks and a high
order model
the CB marks are OPI is also comparable
to that of the smash XY Mark especially
in near ir and far IR colors in summary
the CB Mark not only offers a
significant reduction in size but also
maintains comparable performance metrics
to traditional smash XY marks this makes
it a promising candidate for future
alignment processes particularly when
optimizing scribe Lane space is a
priority without compromising on
performance
in photolithography the process of
ensuring that patterns are accurately
stacked at the same location is divided
into two main tasks alignment and
overlay
while alignment is the act of reading
the alignment marks from a previous
photo process to precisely position the
wafer before exposure overlay is the
task of verifying that the patterns have
been accurately stacked after the
exposure process
the concept of overlay is defined as the
positional accuracy with which a new
lithographic pattern is printed on top
of an existing one on the wafer
this measurement can be taken at any
point on the wafer and is referred to as
overlay error
the term overlay specifically describes
the lateral positioning between layers
that make up integrated circuits
while the overlay error doesn't need to
be exactly zero It Must Fall within
certain tolerances to be acceptable
in practice overlay verification is done
by creating marks on the current layer
that overlap with marks created during
the exposure of the previous layer
the difference in the centers of these
marks allows for positional verification
each measurement Point provides DX and d
y values which quantify the overlay
error
these values can be represented as
vectors on a vector map
the concept of overlay functions through
a feedback mechanism
after the exposure process overlay
errors are measured and used to either
adjust subsequent production Lots or
rework the current wafer to correct
these errors
importantly it's not the raw overlay
error that is fed back into the system
rather parameters derived from the
oafberlay model are used for Corrections
reflecting a targeted approach to
improve overlay control
overlay measurement is typically
performed after the exposure process and
focuses on both interfield and
interfield errors
in asml's Twin scan equipment two-way
for stages are used and usually two
Wafers per lot are measured for overlay
error
this data is then used as feedback for
managing overlay in the current or
subsequent Lots
the measurement is generally conducted
using specialized overlay measurement
equipment commonly provided by companies
like asml and KLA tank core
for example in tsmc foundry's case
overlay management is so critical for
products at the three nanometers
technology node that every wafer is
measured for overlay
if errors are found all Wafers are
reworked and then re-exposed
highlighting the immense importance of
overlay Management in achieving high
production yields
in the field of lithography the
alignment process serves as a critical
preliminary step to accurately position
the patterns on the wafer before
initiating the exposure process
despite its importance alignment by
itself is not sufficient to guarantee
Flawless overlay this insufficiency
arises from a range of factors including
but not limited to variability in the
alignment system and accuracies in
reticle registration and reticle Stage
control imperfections in the lens lens
heating variations in wafer stage
accuracy and wafer stage grid errors in
The Mask process-induced key asymmetry
thermal effects on the wafer sensitivity
to lens aberrations and systematic or
slowly drifting errors
for example during the exposure process
the lens is susceptible to heating which
can alter its refractive index and
consequently introduce errors in the
projected pattern thereby affecting the
overlay's accuracy
similarly the wafer itself May undergo
thermal changes between the alignment
and exposure steps leading to
dimensional alterations that can
compromise overlay accuracy
it's crucial to understand that the
alignment process is designed to make
adjustments at the wafer level not at
the field level
therefore to achieve a more accurate
overlay modeling specific to field
alignment must be separately
Incorporated and fed back into the
exposure process
the goal of overlay modeling is to
create a mathematical framework that
quantifies the impact of various Source
parameters on the total overlay error
initially the model proposed by Perla
focused on linear Source parameters like
translation rotation and magnification
as technology advanced nor Models
Incorporated polynomial terms to address
more complex parameters such as
trapezoids distortions and bows with the
Improvement in exposure systems models
have been further refined to include
parameters of the third order or higher
these mathematical models are integrated
into the software that controls wafer
steppers the machines responsible for
aligning Wafers and converting their
positions to Stage coordinates
it's crucial for these models to be in
sync with the stepper's internal
software and adhere to the physical
principles of the specific type of wafer
stepper in use whether it's a step and
repeat or step and scan system
in the realm of overlay errors models
differentiate between variations that
occur within individual exposure Fields
known as interfield or field term errors
and those that manifest from one
exposure field to another across
different Wafers known as interfield or
wafer term errors overlay measurement
data is typically organized in a map
format and can be sorted into various
categories
uncorrected measurement data is referred
to as raw data data where only the
center of the shot is retained from the
raw data is called inter field data
data at the shot level tiles within the
raw data is known as interfield data
data that can be adjusted through
overlay modeling techniques is termed
model data and data that remains
uncorrectable even after applying
overlay modeling is known as residual
data overlay measurement is pivotal and
semiconductor manufacturing ensuring
precise way for layering
each measurement points overlay can be
depicted as a vector with components
Delta X and Delta y
using the asml twinscan approach a
measurement is taken for each check
organizing the data into raw data Vector
maps and dispersion Maps
to transform the raw overlay measurement
data into correctable components for the
scanner linear regression is employed
techniques such as the least squares and
gaussian elimination help determine
coefficients that minimize residuals
this model encompasses terms like offset
scale and rotation for both the wafer
and reticle
the least squares method stands out for
its computational Simplicity allowing
easy Matrix calculations to determine
model coefficients
another Advantage is its transitivity if
one stepper matches another and the
second match is a third the first will
also match the Third
however this method doesn't minimize
maximum error posing challenges when
synchronizing multiple scanners in a
vast fabrication unit
in the linear model terms like offset
magnification and rotation have distinct
physical implications
derived from the measured DX and d y
overlay values these factors are then
relayed back for exposure side
adjustments
residual errors which don't fit the
linear model can emerge from various
sources such as the scanner stages in
Precision or synchronization issues with
multiple scanners
the offset parameters ox and o y signify
translation errors in the X and Y axes
reflecting the printed Grid's overall
shift compared to the substrate layers
grid
overlay errors at any wafer Point
combined interfield and interfield
errors
it's vital to categorize these errors
since they typically stem from distinct
Origins
for example reticle rotation errors
pertain to reticle alignment whereas
wafer rotation concerns separate
alignments
interfields errors represent overlay
discrepancies at equivalent points in
each exposure field typically at the
center
scale errors denoted by WX and Wy arise
from the scanner's miscalculations and
adjusting for wafer size changes and are
often expressed in parts per million
rotation factors RX at our y determine
if one Grid's rotation aligns with
another
a discrepancy between them indicates an
orthogonality error
intrafield errors on the other hand
fluctuate across each exposure field
they can stem from magnification
discrepancies when wafer size changes
between masking steps
in step and scan systems intrafield
rotation becomes more intricate due to
the radical scanning stages added
component
addressing entry field errors involves
methods like adjusting lens elements
altering the distance between the
reticle and lens rotating the reticle on
its stage and modifying the reticle
stages scanning relative to the wafer
stage to conclude linear
regression-based overlay measurement and
modeling are integral to semiconductor
manufacturing aiding an error
quantification and rectification to
ensure Wafers are layered accurately
managing both enter field and
inter-field errors characterized by
terms such as offset scale and rotation
is crucial for preserving overlay
precision
however as devices continue to scale
down the linear model alone becomes
insufficient for achieving precise
overlay
consequently Advanced non-linear models
are now being employed as extensions to
enhance accuracy until around 2001 the
semiconductor industry primarily relied
on linear models to control overlay
errors
however as technology advanced it became
clear that linear models were no longer
sufficient
the shift to 300 millimeter Wafers
brought about more complex non-linear
distortions often caused by processes
like film deposition and thermal
annealing
this led to the development of high
order correction hoc methods to tackle
these more intricate issues
hoc goes beyond basic linear Corrections
like scaling rotation and translation
it uses a complex model with up to 40
parameters including terms up to the
third order to capture the underlying
distortions more accurately
Advanced lithography systems can have up
to 33 or even 38k parameters per wafer
and field to correct for in respectively
EV and duv systems
for example the right figure shows
significant Improvement of overlay
accuracy using only 12 high-order terms
and nine wafers
non-linear overlay errors although
generally smaller than their linear
counterparts can't be ignored
one common source is matching errors
which occur when multiple scanners are
used
these errors can often be corrected to
some extent
another source is way for heating during
exposures initially observed in online
exposures but becoming more significant
in ARF immersion lithography
Wafers can also undergo non-linear
distortions due to Rapid thermal
processing which traditional linear
alignment methods can't correct
trapezoid errors are another type of
non-linear overlay error
they occur when the reticle is not
perfectly aligned with the optical axis
causing varying magnification across the
exposure field
however neurlands designs that are
telecentric on both the wafer and
reticle sides have eliminated these
errors
asml has developed sophisticated
techniques such as high order process
correction hopc and high order wafer
alignment h-o-w-a to meet the stringent
demands of contemporary semiconductor
Manufacturing
how specializes in inter-field high
order global grid modeling offering a
field-based correction per wafer
this is particularly useful for aligning
the wafer in a manner that accounts for
higher order distortions thereby
enhancing overall overlay accuracy
for interfield overlay correction hopc
and correction for exposure CP are
employed
hopc focuses on process correction based
on interfield high order global grid
modeling offering field-based correction
determined by the hopc model and field
location
on the other hand CPA is designed to
apply a six-parameter intrafield
correction for each exposure
this is especially beneficial when the
intrafield overlay exhibits a non-linear
fingerprint which could be attributed to
various factors such as wafer processing
or reticle pattern placement errors for
intrafield overlay correction ihopc is
utilized
this method is specifically designed for
per exposure correction based on
inter-field high order modeling
it is identical for all fields and is
particularly effective for compensating
errors that are unique to each exposure
field offering a more nuanced and
precise correction
the correction data generated by these
Advanced Techniques can be employed for
both feedback and feed forward
mechanisms
this not only improves the overlay
accuracy for the current batch of Wafers
but also enhances the overlay for
subsequent batches in the semiconductor
manufacturing industry the reliability
of overlay measurement tools is a
critical concern and it's evaluated
using several key performance indicators
kpis
among these kpis total measurement
uncertainty tmu and movement acquisition
measurement mam are particularly
significant
starting with the equipment different
companies have their Flagship overlay
measurement tools
asml offers the yield star which employs
diffraction-based overlay dbo technology
KLA tanker has the Archer series which
uses both imaging-based overlay IBO and
dbo methods
South Korea's auras offers ebo-based
tools like the ol700n and ol800n
each of these tools has specific
performance metrics
for instance the Archer 700 HP has a
Precision of 0.12 nanometers Tis of 0.15
nanometers tmu of 0.3 nanometers and a
man time of 0.2 seconds
tmu is a comprehensive metric that
encapsulates various factors affecting
measurement reliability
it's calculated as the square root of
the sum of dynamic repeatability to
three sigma tis mean and Tool matching
the tmu is generally considered to be
one-tenth of the overlay control budget
especially for challenging use cases and
advanced technology nodes
however it's important to note that tmu
alone doesn't provide a complete picture
of measurement reliability
accuracy must also be verified often
requiring direct measurement on the cell
tool induced shift tis is used to assess
the reliability of overlay measurements
it involves taking measurements at 0
degrees and 180 degrees rotations of the
wafer to identify any pattern in
asymmetry or anomalies in the tool
the quality criteria for tis include the
three sigmatis and the residual after 10
parameter modeling
Dynamic repeatability refers to the
consistency of measurements at the wafer
level
it's an essential metric because it
indicates how reliably the tool can
reproduce measurements which is crucial
for process control
for accuracy Advanced metrics like
humerit are being developed
cumerit measures the severity of Target
asymmetry and can be statistically
analyzed
this is particularly useful for data
correction and significantly enhances
the overall reliability of overlay
measurement tools
man time is another crucial kpi
it represents the time it takes to
measure one target move and then prepare
for the next measurement
this is particularly important for
inline Metrology where process control
is essential
the focus here is on measurement
consistency and the ability to be robust
against process variations which is
vital for reducing Metrology uncertainty
in summary the reliability of overlay
measurement tools is a multifaceted
issue that requires consideration of
various kpis like tmu tis Dynamic
repeatability and man time
while tmu provides a comprehensive view
it must be complemented by direct
accuracy checks and other metrics to
ensure robust and reliable overlay
measurements overlay measurement is
crucial in semiconductor manufacturing
because direct measurement of circuit
patterns isn't possible
to work around this overlay keys are
used which are located on the Scribe
line
these keys are placed at the boundary
between dies during the wafer
photolithography process and are removed
when the final packaging stage is
reached
during the r d phase the Scribe Lane is
set y to accommodate various test items
however in the mass production phase the
lane width is minimized to include only
the essential marks needed for process
control
the alignment Mark is printed solely on
the previous layer while overlay marks
are printed on both the current and
previous layers to ensure accurate
measurement
two primary methods are employed for
optical overlay Metrology image-based
overlay IBO and diffraction based
overlay DPO
IBO has been the go-to method for many
years
it uses a CCD camera to capture
intensity data which is then used to
determine the position of the marks
this is somewhat analogous to how our
eyes perceive positions
to facilitate this image-based
verification a step can be created in
the previous layer by forming a trench
or a Mesa shape
alternatively a cell-like pattern can be
used to generate a contrast in materials
various types of IBO marks exist such as
box and box Bib and Advanced Imaging
Metrology aim
the BRB Mark has been in use for a long
time and it provides an intuitive way to
measure overlay accuracy by looking at
the horizontal and vertical distances
between the boxes on the previous and
current layers
the aim mark on the other hand is used
to increase resolution
there's also a variant known as aaaim
which allows for the assessment of
positional relationships among three
different processes
IBO has its advantages and disadvantages
on the plus side it is less sensitive to
variations in the underlying film
however it is vulnerable to deformations
caused by etching and CMP processes
moreover as technology continues to
advance IBO faces challenges in meeting
overlay requirements
this is because lens aberrations
illumination imperfections and
variations in wafer processes can
introduce an offset known as
tool-induced shift tis in IBL
measurements
because of these limitations especially
in the era of single nanometer overlay
accuracy the bib Mark is reaching its
limits
this has led to the introduction of
diffraction-based overlay or simply dbo
dbo relies on the intensity of Lights
scattered from a grading over grading
Target to provide overlay information
the overlay value is calculated based on
an intensity contrast ratio dbo offers a
unique set of pros and cons
one of its advantages is that it
requires a smaller Vernier size on the
Scribe line as the marks for both the
previous and current layers are
generated with overlapping positions and
identical sizes
additionally DBL outperforms IBO in
terms of total measurement uncertainty
tmu and is immune to Optical aberrations
leading to Superior tool-induced shift
tis performance
it is also less susceptible to
deformations from etching and CMP
processes and excels in measurement
repeatability however dbo has its
drawbacks
unlike IBO it doesn't provide a real
image for verification making it
challenging to confirm the actual image
it is also sensitive to variations in
the underlying film layers
the design of the key is particularly
important as dbo relies on light
diffraction for its measurements
in summary both IBO and dbo have their
merits and drawbacks
but as the industry moves towards more
advanced technology nodes dbo is
increasingly being considered the future
of overlay Metrology due to its lower
tmu and better Precision in
semiconductor manufacturing getting the
alignment and overlay marks right is
essential for accurate layering of the
wafer
these marks can get compromised during
various stages like deposition etching
and CMP
when that happens it leads to asymmetry
which in turn causes alignment and
overlay errors
the scanner's alignment system plays a
crucial role here
its performance is affected by many
factors in the manufacturing process
such as the type of film being deposited
the Coatings used and the etching and
polishing processes
that's why lithography Engineers work on
optimizing these alignment targets
they consider various aspects like the
size of the targets the type of film
used how deep to etch and the polishing
process
now let's delve into the specific
challenges and how to address them
especially those caused by physical
vapor deposition PVD and CMP
during PVD the process of sputter
depositing metals can cause Edge
asymmetry in the overlay targets
this happens because the metal ions get
partially blocked or shadowed by the
existing layout of the alignment or
overlay mark
this shadowing effect is more pronounced
near the wafer Edge making the thickness
of the deposited film non-uniform
this leads to shifts in how the Mark is
seen often showing up as errors that
affect the whole wafer the problem gets
even more complicated when you consider
the different shapes and sizes on the
substrate especially when comparing
large structures used for alignment in
the smaller critical features in the
final product
to address this Engineers check if these
asymmetries are consistent
if they are they calculate overlay off
sets offline and use them for
Corrections
another approach is using a technique
called MRC or misreading correction
this involves measuring the overlay
within the cell and the post-etching
inspection stage and then feeding this
information back into the
photolithography process
this helps in realigning the patterns
and reducing errors caused by Edge
asymmetry
CMP presents its own set of challenges
CMP is designed to create highly
planarized surfaces on the wafer
while this is beneficial for lithography
reducing thin film effects and
increasing the depth of focus it poses a
significant challenge for overlay
accuracy
the planarization process tends to
reduce the contrast of alignment targets
making them harder to detect in some
cases
another issue with CMP is the
introduction of asymmetry and erosion of
the marks during the polishing process
the wafer is rotated in Only One
Direction while polishing which can lead
to uneven wear and consequently
asymmetry in the alignment marks
this is particularly problematic when
the alignment marks are wide as this
exacerbates CMP erosion it's important
to note that this issue isn't limited to
metal CMP processes it's a challenge
that occurs in all types of CMP
processes including those for shallow
trench isolation to counteract these
issues several strategies are used one
is to change the size or shape of the
alignment marks
another is to get polishing Engineers
involved in improving the overlay
they might change the polishing pads to
harder ones to reduce errors
scanner manufacturers are also doing
their part by updating their alignment
systems with new algorithms and better
illumination techniques
there are even new technologies like
Orion sensors that are designed to read
alignment marks regardless of any
asymmetry offering another way to tackle
the challenges posed by CMP
so in a nutshell both PVD and CMP
introduce their own sets of challenges
in maintaining Accurate Alignment and
overlay
but with targeted strategies like MRC
for PVD and various process
modifications for CMP these challenges
can be managed effectively traditionally
overlay air has been gauged using
overlay marks but these marks often fail
to accurately represent the true
position of the device or cell
this inaccuracy stems from the
limitations of traditional Optical
overlay Metrology methods like Imaging
based overlay IBO and diffraction-based
overlay DPO
one of the first significant issues is
the ADI to AEI offset which is the
difference between overlay errors
measured at the after develop inspection
ADI and after etch inspection AI stages
this offset is primarily due to
process-induced Overlay effects
for example during deposition the
thickness of the film deposited on the
sidewall can vary
in the etching process a slope can
develop at the bottom of the overlay
Mark affecting its geometry
during the CMP stage asymmetric erosion
of the mark can occur due to the wafer
rotating in a single Direction
these process-induced variations
collectively lead to distortions and
asymmetry in the overlay marks
compromising measurement accuracy
the second issue is the discrepancy
between overlay errors measured from 8di
and AEI overlay marks and the actual
device chip
this discrepancy known as Metrology to
device offset NTD has become more
pronounced with technological
advancements
several new error sources such as
etch-induced overlay and stress-induced
Indie overlay contribute to this offset
minimizing MTD is crucial because Fab
overlay is generally controlled by a
run-to-run control of ADI overlay
moreover measuring the overlay error
directly on the main device chip at the
AEI stage would reflect a more accurate
on product overlay opio
the third issue is related to intrafield
high order process correction ihopc
traditional methods struggle to achieve
good ihopc due to the limited number of
overlay marks and their uneven
distribution across the field
particularly affecting the overlay at
the outermost chips on the wafer
to address these challenges new
methodologies like in-device Metrology
IDM and in cell overlay are emerging
these methods aim to measure overlay
directly within the device or cell thus
bypassing the limitations of traditional
scribe Lane marks
however these methods are not without
their challenges
high voltage sem methods can potentially
cause electron damage and Optical CD
methods using optical scattering have
issues like large beam spot sizes
despite these challenges these new
methodologies hold promise for a more
accurate representation of actual
overlay performance
another technique gaining traction is
misreading correction MRC which corrects
discrepancies between ADI key overlay
measurements and AEI and cell overlay
measurements
MRC addresses various causes for these
discrepancies such as differences in
pattern size and position as well as
process-induced overlay effects in
summary as device Dimensions continue to
shrink the need for precise and accurate
overlay control is escalating
traditional methods are hitting their
limitations and new approaches like in
cell overlay and IDM are stepping in to
fill the Gap minimizing key factors like
the ADI to AEI offset and MTD is
essential for Effective overlay control
techniques like MRC are also becoming
indispensable for correcting
discrepancies and enhancing overlay
accuracy overlay measurement is a
critical aspect of semiconductor
manufacturing especially in defect
limited yield and high volume
manufacturing of modern technology nodes
the process involves sampling that
captures data for specific Wafers
including both grid and interfield error
components
due to high-capital equipment costs and
the impact on cycle time it's not
feasible to measure every single wafer
or lot
therefore A system that can provide
optimal feedback based on this limited
data is essential
for non-critical layers usually two
Wafers per lot are measured considering
asml's twin stage system and feedback is
provided for the subsequent Lots
Advanced feed forward control May
significantly reduce lot to lot and
wafer to wafer variations and rework
rate
feedback optimization is also crucial in
minimizing overlay error and the system
quickly responds to shifts and drifts to
maintain the desired Target
however it may become susceptible to
random noise thus degrading stability
for critical layers all Wafers are
measured reworked and then feed forward
is applied to the same wafer of the same
lot
the overlay measurement map is used to
make corrections to bring the overlay of
subsequent Lots closer to zero
however unlimited compensation is not
possible leading to the existence of
uncorrectable maps
the overlay error is divided into
correctable and non-correctable or
residual parts
the computation phase involves
regression and decision-making steps
advanced process control APC is an
automated system that allows for process
control without human intervention
it is primarily used for overlay
compensation in photo processes
one of the key features of APC is run to
run r2r control
APC feedback and feed forward schemes
are essential for high volume
manufacturing as they significantly
reduce lot to lot overlay variation
the system is designed to respond
correctly even when large changes are
observed such as after preventative
maintenance or other tool interventions
the basic formula for r2r control is f
equals a plus b plus EF where f is the
final feedback calculation value a is
the exposure equipment input value for
the current steps feedback Lot B is the
overlay measurement value for the
current steps feedback lot e is the
exposure equipment input value when an
align layer exists and F is the exposure
equipment input value during the Align
layer for the feed forward lot
the basic logic is to add the overlay
read feedback value B to the input value
a
the concept of feed forward is also
crucial
it involves using the current layer's
exposure results to inform the next
layer's exposure parameters especially
about the interfield terms
this is particularly important when the
overlay error is not perfectly zero
requiring additional compensation
between the Align layer and the target
layer in the case of field parameters
the values change due to the photo
process therefore lots that do not read
the overlay are assumed to have received
the appropriate input value during the
previous align layer
in summary overlay correction is the
multifaceted process that involves
intricate steps in systems like APC
it requires a nuanced balance of
feedback and fee forward mechanisms all
while navigating the Practical
limitations of sampling and Equipment
constraints
Advanced modeling alignment optimization
and advanced fee forward Have Been
instrumental in meeting the tight
overlay requirements for high volume
manufacturing of modern technology nodes
a knowledge-based APC methodology is
applied for overlay control optimizing
the APC strategy in step and scan or
simply scanner systems use in
semiconductor manufacturing field
positions can sometimes be offset when
scanned in opposite directions leading
to what are commonly known as scan-up
scan down susd errors
similar errors term step left step right
slsr errors occur when the stages are
moved in a direction perpendicular to
the scan
these errors become particularly
relevant when multiple tools are used
such as in mixed mode overlay MMO
scenarios
however when all layers are Exposed on a
single Scanner with the same stepping
pattern these errors tend to cancel out
this is especially true for duv to duv
Overlay as the gravitational induced
sagging of the reticle cancels out in
these cases
to measure these errors overlapping
fields are used particularly in the
Scribe Lane areas at the field or shot
edges
susd errors lead to measurable overlay
errors in the scan directions
the pellicle-induced overlay fingerprint
shows a strong susd Behavior which can
be Quantified using specific pellicle
tests
in deep UV ARF immersion lithography
pellicle bending is another source of
overlay error that shows a strong susd
Behavior
during the exposure process the scanner
moves the wafer in a zigzag pattern
under the lens
the pellicle a thin foil stretched in a
frame to protect the mask deforms due to
pressure variations during its
acceleration
this deformation causes light to refract
resulting in a slight displacement of
the image on the wafer
a model running on the scanner can
predict this pellicle bending and
calculate the needed overlay corrections
to apply during exposures
this has been effective in keeping duv
to duv Overlay errors under a nanometer
however when applying cross MMO between
euv and duv non-correctable Stitch
overlay errors have been observed
these are primarily due to differences
in lens and reticle clamping between euv
and duv equipment
euv reticles do not suffer from
gravitational induced sagging due to the
clamping Force applied over the full
area of the radical making the effect
uncancelable and cross-matching cases
to address these challenges several
ongoing Solutions are being developed
the first is zeiseric a technology that
impose a fingerprint offset into the
reticle when applying UV MMO to duv
during Masky beam exposure
the second is litho booster a new
overlay tool for indirect measurement
it transitions from relative measurement
which compares the edge to edge
positions of parent-child boxes to
Absolute measurement which compares the
center to Center positions of boxes
the goal of these ongoing developments
is to achieve a cross-matched machine
overlay below 2.0 nanometers required
for the introduction of euv and high
volume Manufacturing
today we've journeyed through an
expansive topic so let's pause for a
summary
we kicked off with overlay error
discussing Essential Elements like
scribe Lane alignment Mark overlay mark
on product overlay single machine
overlay mix machine overlay and the
vital importance of total measurement
uncertainty
we also examined a holistic approach to
control overlay by understanding its
classification and hierarchy
next we ventured into alignment and
leveling
We examined the asml twin scan
technology and in its different phases
measure side expose side and metroframe
we navigated through the life of a wafer
covering zeroing interferometer encoder
reticle and Stage align and leveling
we also delved into specialized topics
like UV level sensor Global leveling
Circle wafer cmap and focus spot
monitoring
we explored course wafer align find way
for a line and the role of sensors like
Athena Smash and Orion
additionally we discussed various marks
such as Athena smash CB and Blossom
along with their key performance indices
like WQ MCC Repro ropi and rpn
lastly we zeroed in on overlay
we talked about overlay vector
interfields and interfield terms
we explored linear and non-linear models
covering wafer term with h-o-w-a CP hopc
and field term with ihopc we also looked
at overlay measurement techniques
covering them time tmu tool-induced
shift and accuracy metrics like humerit
and test Sigma
we reviewed different types of overlay
marks specifically image-based overlay
and diffraction based overlay
we discussed overlay correction methods
process dependent overlay effects and
Mark asymmetry caused by PVD and CMP
processes
we also covered in device Metrology
topics like in cell overlay marked a
device offset and misreading correction
we concluded with advanced process
control methods like feedback and feed
forward and specific issues related to
UV to duv cross MMO and susd fingerprint
that concludes our in-depth exploration
of alignment and overlay that was quite
a deep dive wasn't it
today we unpacked the intricacies of
lithography alignment leveling and
overlay a Cornerstone of semiconductor
Manufacturing
while it may have been technical we
trusted enriched your understanding
thank you for journeying with us through
the nuances of photolithography
there's more to uncover and we'll keep
peeling back the layers in upcoming
episodes
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